1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a method for manufacturing a multi-thickness gate dielectric layer used as a gate oxide for semiconductor devices.
2. Description of the Related Art
in the fabrication of a semiconductor device, devices, such as various kinds of transistors, are integrated onto a common substrate. For example, system-on-chip (SOC) devices are formed of various transistors or devices which are integrated on the same substrate. Namely, a low standby power device, a high performance device, an I/O device, and an analog device are integrated on the same substrate to constitute a single semiconductor device, e.g., an SOC device.
It is preferable that each of the various kinds of transistors includes an appropriate gate oxide, or a gate dielectric layer, having a thickness that is appropriate for operation thereof. For instance, in the case of an I/O device, an oxide layer of approximately 50 Å or more in thickness is required to form a gate dielectric layer of a transistor, although the thickness of the gate dielectric layer depends on the design rule or the integration level of the semiconductor device. For clarity of explanation, such thickness of the gate dielectric layer is understood as an equivalent oxide thickness parameter (Teq). However, in a cell or core of a semiconductor device such as a transistor constituting a static random access memory (SRAM), it is also preferable to use a gate dielectric layer of a thickness of approximately 30 Å or less so that the transistor can perform operations optimally. That is, it is necessary that a gate dielectric layer having different thicknesses be formed on the same substrate constituting a single semiconductor device for regions of the device that include transistors that serve different functions.
Furthermore, different operating voltages are applied to devices that serve different purposes. For example, an operating voltage of approximately 3.3V is applied to a transistor adopted for an I/O device, while a relatively low operating voltage of approximately 2.5V or 1.0V may be applied to a transistor adopted for a device of a core or cell. Thus, each of the transistors preferably has a gate dielectric layer of a respectively different thickness so as to be suitable for the operating voltage.
It is presently known that a method for manufacturing a gate dielectric layer having different thicknesses may be realized by a dual strip technique. According to the dual strip technique, a silicon oxide layer is formed on a semiconductor substrate to a relatively thick thickness suitable for a transistor or other devices that require a thick gate dielectric layer. Thereafter, a portion of the thick silicon oxide layer is selectively removed from the semiconductor substrate, where a device required for a relatively thinner gate dielectric layer will be embodied, to partially expose a surface of the semiconductor substrate. A new silicon oxide layer is then formed to a relatively thinner thickness on the exposed surface of the semiconductor substrate. In this manner, a gate dielectric layer having different thicknesses in different regions of the device is formed.
However, in the method for manufacturing the gate dielectric layer having two different thicknesses using the above dual strip technique, it is difficult to adjust and control the thicknesses of the gate dielectric layer. For instance, because the same silicon oxide layer is grown twice, it is difficult to uniformly form the gate dielectric layer. That is, when a second silicon oxide layer is grown to a relatively thin thickness following the selective stripping, the thickness of the pre-formed thick silicon oxide layer may be unevenly changed. This is because the same silicon oxide layer is used twice for the gate dielectric layer to achieve the different thicknesses. In this case, the thickness uniformity of the gate dielectric layer is degraded, and this results in deterioration of characteristics of the resulting transistors. In particular, when a difference in the thickness between a thick portion and a thin portion of the gate dielectric layer is comparatively small, it becomes more difficult to control the thickness of the gate dielectric layer.